Configure-time gate for the PR-12 component set
(&ocean_forcing_nml enable_components). init runs before the
namelist gate is known, so allocation happens HERE rather than in
init: enable = .false. (default) leaves use_components
false and allocates nothing — bit-identical, zero extra device
memory. enable = .true. allocates the full component set
(source=0.0_wp) and flips the gate so
ocean_surface_flux_assemble stops early-returning. Must be
called BEFORE enter_data (rdb_ocean_state.F90’s orchestrator)
so the freshly-allocated arrays get mapped. Re-entrant: calling
again with a different enable deallocates first.
| Type | Intent | Optional | Attributes | Name | ||
|---|---|---|---|---|---|---|
| class(ocean_surface_flux_t), | intent(inout) | :: | this | |||
| type(hgrid_t), | intent(in) | :: | grid | |||
| logical, | intent(in) | :: | enable |
subroutine ocean_surfflux_set_components(this, grid, enable) !! Configure-time gate for the PR-12 component set !! (`&ocean_forcing_nml enable_components`). `init` runs before the !! namelist gate is known, so allocation happens HERE rather than in !! `init`: `enable = .false.` (default) leaves `use_components` !! false and allocates nothing — bit-identical, zero extra device !! memory. `enable = .true.` allocates the full component set !! (`source=0.0_wp`) and flips the gate so !! `ocean_surface_flux_assemble` stops early-returning. Must be !! called BEFORE `enter_data` (`rdb_ocean_state.F90`'s orchestrator) !! so the freshly-allocated arrays get mapped. Re-entrant: calling !! again with a different `enable` deallocates first. class(ocean_surface_flux_t), intent(inout) :: this type(hgrid_t), intent(in) :: grid logical, intent(in) :: enable call ocean_surfflux_dealloc_components(this) this%use_components = enable if (enable) call ocean_surfflux_alloc_components(this, grid) end subroutine ocean_surfflux_set_components